The present invention relates generally to output circuits, and more particularly to a method and apparatus for a comparator output controlled circuit.
A comparator is a circuit that senses the difference between its two inputs and changes its output state depending on which of the inputs is higher in voltage. In CMOS (Complementary Metal Oxide Semiconductor) technology, as the comparator output makes a transition, there is current that flows for a short time when both NMOS (Negative Channel MOS) and PMOS (Positive Channel MOS) transistors are on. During a change in output state, a comparator, or any other analog or digital circuit, may conduct significant current from the power source.
Electronic circuits are being pressed into operation at lower supply voltages and currents. For some very low power comparators, the switching or transition current may be large relative to the static quiescent current of the comparator. In low-power applications, the DC switching current is conducted for an especially long period of time, because of the slow propagation delay of an output state change. Also because the comparator has a large output driver to drive a large load, the DC switching current (magnitude) can become quite large. A high slew rate occurs in existing technologies as comparator output drivers change the output from one state to the other. Thus, in very low-power applications, it would be desirable to limit the switching current and the slew rate of the comparator output, in order to limit power consumption.
Existing technologies"" attempts to implement output control have not offered solutions relevant to the very low-power environment. Output control circuits have been designed for high-speed buffers, implementing multiple small output drivers connected in parallel and staging their turn-on times in a staggered way. These circuits are to reduce ground/supply bounce primarily. However, these circuits fail to address the problems of excessive power consumption and slew rate.
Other existing technologies"" output control circuits are slew-rate-limited, but not very low-power. One example implements two parallel output drivers, one slew-rate-limited and the other strong for DC performance. A strongly-switching output driver is disadvantageous for very low power applications because of the high slew rate. A high slew rate of the output driver may cause an increase in the total current used in the system because it may lead to ground or supply bounce, and charge/discharge of Vddxe2x88x92Vss capacitance either on or off chip, e.g., decoupling capacitors. A high slew rate output driver may also couple noise into sensitive high impedance input nodes that may be present in very low power circuits. For the aforementioned reasons a slower, controlled (current-limited) slew rate is preferred for very low power circuits. However, existing technologies"" low power drivers, which are slew-rate-limited, may be ineffective in a very-low-power application because, at least in part, their slew-rate control circuit does not use feedback to adjust itself to achieve optimal slew-rate.
Existing technologies"" output control circuits do limit xe2x80x9ccrow-barxe2x80x9d current, i.e. Class-A CMOS current; for existing technologies"" purposes, a limited conduction of crow-bar current is acceptable. For very low-power applications, no crow-bar current ought to be conducted. None of the existing technologies"" output control circuits substantially eliminate crow-bar current.
The invention overcomes the above-identified problems as well as other shortcomings and deficiencies of existing technologies by providing a method and apparatus for a digital output driver where low power operation is desirable.
In accordance with an exemplary embodiment of the present invention, a low-power digital output (logic low or logic high output) driver having a control circuit comprising a break-before-make circuit and an output buffer connected to the break-before-make circuit, the output buffer adapted for outputting digital logic levels.
In accordance with another exemplary embodiment of the present invention, a low-power digital output (logic low or logic high output) driver having a control circuit comprising a break-before-make circuit, a slew-rate control circuit connected to the break-before-make circuit, and an output buffer connected to the slew-rate control circuit, the output buffer adapted for outputting digital logic levels. The slew-rate control circuit comprises a first capacitor, a second capacitor connected to the first capacitor, and a feedback element connected to the first capacitor and the second capacitor.
In accordance with a further exemplary embodiment of the present invention, a low-power digital output (logic low or logic high output) driver having a control circuit comprising a current limited input amplifier with low output impedance and minimal switching current, a break-before-make circuit connected to the current limited input amplifier, and an output buffer connected to the break-before-make circuit, the output buffer adapted for outputting digital logic levels.
In accordance with still a further exemplary embodiment of the present invention, a low-power digital output (logic low or logic high output) driver having a control circuit comprising a current limited input amplifier and an output buffer adapted for outputting digital logic levels, wherein the output buffer is connected to the current limited input amplifier.
In accordance with yet a further exemplary embodiment of the present invention, a low-power digital output (logic low or logic high output) driver having a control circuit comprising a current limited input amplifier, a slew-rate control circuit comprising a first capacitor, a second capacitor connected to the first capacitor, and a feedback element connected to the first capacitor and the second capacitor, wherein the slew-rate control circuit is connected to the current limited input amplifier, and an output buffer adapted for outputting digital logic levels, wherein the output buffer is connected to the slew-rate control circuit.
In accordance with yet another exemplary embodiment of the present invention, a low-power digital output (logic low or logic high output) driver having a control circuit comprising a current limited input amplifier with low output impedance and minimal switching current, a break-before-make circuit connected to the current limited input amplifier, a slew-rate control circuit connected to the break-before-make circuit, and an output buffer connected to the slew-rate control circuit, the output buffer adapted for outputting digital logic levels. The slew-rate control circuit comprises a first capacitor, a second capacitor connected to the first capacitor, and a feedback element connected to the first capacitor and the second capacitor.
In addition, the present invention is also directed to methods of operation for low-power output control comprising the steps of delaying a state change of an output buffer of the circuit with a break-before-make circuit and outputting digital logic levels with the output buffer, wherein the output buffer is connected to the break-before-make circuit.
The present invention is further directed to methods of operation for low-power output control comprising the steps of amplifying an input bias of the circuit with a current limited input amplifier and outputting digital logic levels with the output buffer, wherein the output buffer is connected to the current limited input amplifier.
An advantage of the present invention is that it requires few components, none of which consume much power. Another advantage is that the method of slew-rate control presented in this invention uses feedback to regulate the slew rate of the output stage. Thus, the slew-rate control method is more precise and consistent than existing technologies"" methods, and is applicable to very low power circuits.
A further advantage of the present invention is that it conducts substantially no crow-bar current and minimal switching current, essential aspects for very low power design.
Features and advantages of the invention will be apparent from the following description of the embodiments, given for the purpose of disclosure and taken in conjunction with the accompanying drawing.